Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

US7960794B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Brian S. Doyle · Portland, US
• Suman Datta · Beaverton, US
• Been-Yih Jin · Lake Oswego, US
• Nancy Zelick · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Dec 20, 2007
• Grant date: Jun 14, 2011
• Expiry date: Feb 4, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/933

Abstract

A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.