Stage yield prediction
US7962864B2 · kind B2 · utility
8Cited by
16References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Jul 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.