Fabricating vias of different size of a semiconductor device by splitting the via patterning process

US7977237B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Feustel · Dresden, DE
• Thomas Werner · Radebeul, DE
• Kai Frohberg · Meißen, DE

Key dates

• Filing date: Sep 30, 2010
• Grant date: Jul 12, 2011
• Expiry date: Sep 30, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.