Inventor · Dresden, DE

Frank Feustel

53Patents
6h-index
32Co-inventors
68Inventor score

Filing activity: Jan 31, 2005 → Apr 25, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US8048811B2 Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material Electricity 152 Active
US7928004B2 Nano imprint technique with increased flexibility with respect to alignment and feature shaping Electricity 8 Active
US7932166B2 Field effect transistor having a stressed contact etch stop layer with reduced conformality Electricity 7 Active
US8399335B2 Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features Electricity 7 Active
US7800106B2 Test structure for OPC-related shorts between lines in a semiconductor device Electricity 7 Active
US7977237B2 Fabricating vias of different size of a semiconductor device by splitting the via patterning process Electricity 7 Active
US8399352B2 Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions Electricity 6 Active
US7764078B2 Test structure for monitoring leakage currents in a metallization layer Electricity 5 Active
US8193086B2 Local silicidation of via bottoms in metallization systems of semiconductor devices Electricity 5 Active
US8357610B2 Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics Electricity 5 Active
US8080866B2 3-D integrated semiconductor device comprising intermediate heat spreading capabilities Electricity 5 Active
US7915170B2 Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge Electricity 4 Active
US7741191B2 Method for preventing the formation of electrical shorts via contact ILD voids Electricity 4 Active
US8293641B2 Nano imprint technique with increased flexibility with respect to alignment and feature shaping Electricity 4 Active
US7306976B2 Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly Electricity 4 Expired
US8173538B2 Method of selectively forming a conductive barrier layer by ALD Electricity 3 Active
US7989352B2 Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics Electricity 3 Active
US9455232B2 Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure Electricity 3 Active
US8859398B2 Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge Electricity 3 Active
US7705352B2 Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias Electricity 3 Active
US8377820B2 Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size Electricity 3 Active
US8241973B2 Method for increasing penetration depth of drain and source implantation species for a given gate height Electricity 2 Active
US8786088B2 Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction Electricity 2 Active
US7879709B2 Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structure Electricity 2 Active
US8039398B2 Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.