Semiconductor device having additional capacitance to inherent gate-drain or inherent drain-source capacitance

US7977737B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Armin Willmeroth · Friedberg, DE
• Winfried Kaindl · Unterhaching, DE
• Carolin Tolksdorf · Ebersberg, DE
• Anton Mauder · Kolbermoor, DE
• Holger Kapels · Holzkirchen, DE
• Gerald Deboy · Klagenfurt, AT
• Franz Hirler · Isen, DE

Key dates

• Filing date: Mar 6, 2008
• Grant date: Jul 12, 2011
• Expiry date: Sep 9, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/13091

Abstract

A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.