Grain boundary blocking for stress migration and electromigration improvement in CU interconnects
US7989338B2 · kind B2 · utility
6Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2005 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76864
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.