Patent · US Active

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics

US7989352B2 · kind B2 · utility

3Cited by

4References

13Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Frank Feustel · Dresden, DE
Kai Frohberg · Meißen, DE
Thomas Werner · Radebeul, DE

Key dates

Filing date	Apr 4, 2007
Grant date	Aug 2, 2011
Priority date	—
Expiry date	Nov 11, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76825
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.