Integration of high voltage JFET in linear bipolar CMOS process
US7989853B2 · kind B2 · utility
2Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Apr 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.