Integrated circuit packaging system having a cavity
US7989950B2 · kind B2 · utility
22Cited by
48References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2008 |
| Grant date | Aug 2, 2011 |
| Priority date | — |
| Expiry date | Jun 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.