Poly profile engineering to modulate spacer induced stress for device enhancement
US7993997B2 · kind B2 · utility
3Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 25, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.