Transistor device with two planar gates and fabrication process
US7994008B2 · kind B2 · utility
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3References
12Claims
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Key dates
| Filing date | Jan 26, 2007 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.