Semiconductor devices having faceted silicide contacts, and related fabrication methods
US7994014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Aug 9, 2011 |
| Priority date | — |
| Expiry date | May 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.