Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process

US7998823B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Carsten Peters · Dresden, DE
• Kai Frohberg · Meißen, DE
• Ralf Richter · Dresden, DE

Key dates

• Filing date: Sep 21, 2006
• Grant date: Aug 16, 2011
• Expiry date: Aug 23, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0151
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.