Memory cell structure and method for fabrication thereof
US7999300B2 · kind B2 · utility
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34References
22Claims
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Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Aug 16, 2011 |
| Priority date | — |
| Expiry date | Oct 17, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.