SRAM with read and write assist
US8004907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2009 |
| Grant date | Aug 23, 2011 |
| Priority date | — |
| Expiry date | Sep 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.