Memory with read cycle write back
US8009489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2009 |
| Grant date | Aug 30, 2011 |
| Priority date | — |
| Expiry date | Nov 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.