Patent · US Active

Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension

US8012820B2 · kind B2 · utility

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Key dates

Filing dateMar 21, 2011
Grant dateSep 6, 2011
Priority date
Expiry dateMar 21, 2031

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038

Abstract

A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.