Three-dimensional networking design structure
US8019970B2 · kind B2 · utility
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14References
15Claims
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Key dates
| Filing date | Nov 28, 2007 |
| Grant date | Sep 13, 2011 |
| Priority date | — |
| Expiry date | Mar 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/145
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable medium used in a design process includes a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements; one or more networking layers disposed between the processing layers, the network layer comprised of one or more networking elements, wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements and each networking element may provide network access to a plurality of other computing elements through a single hop of the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.