Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
US8026539B2 · kind B2 · utility
6Cited by
1References
23Claims
0Family size
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Key dates
| Filing date | Feb 18, 2009 |
| Grant date | Sep 27, 2011 |
| Priority date | — |
| Expiry date | Mar 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.