Semiconductor device with stressed fin sections, and related fabrication methods
US8030144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2009 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Oct 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.