Flash memory programming and verification with reduced leakage current
US8031528B2 · kind B2 · utility
1Cited by
20References
20Claims
0Family size
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Key dates
| Filing date | Sep 11, 2009 |
| Grant date | Oct 4, 2011 |
| Priority date | — |
| Expiry date | Sep 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.