Methods for fabricating bulk FinFET devices having deep trench isolation
US8039326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Oct 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.