Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

US8039335B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Sven Beyer · Dresden, DE
• Manfred Horstmann · Dresden, DE
• Patrick Press · Dresden, DE
• Wolfgang Buchholtz · Radebeul, DE

Key dates

• Filing date: Jan 13, 2011
• Grant date: Oct 18, 2011
• Expiry date: Jan 13, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.