Inventor · Dresden, DE

Patrick Press

15Patents
4h-index
23Co-inventors
56Inventor score

Filing activity: Aug 30, 2001 → Jul 16, 2012

Most-cited inventions

PatentTitleAreaCited byStatus
US7741167B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Electricity 18 Active
US8791509B2 Multiple gate transistor having homogenously silicided fin end portions Electricity 17 Active
US8247281B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers Electricity 9 Active
US7799682B2 Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor Electricity 7 Active
US6548378B1 Method of boron doping wafers using a vertical oven system Chemistry; Metallurgy 3 Expired
US7605045B2 Field effect transistors and methods for fabricating the same Electricity 3 Active
US8039335B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Electricity 2 Active
US7893503B2 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Electricity 2 Active
US8293610B2 Semiconductor device comprising a metal gate stack of reduced height and method of forming the same Electricity 2 Active
US7745334B2 Technique for locally adapting transistor characteristics by using advanced laser/flash anneal techniques Electricity 2 Active
US7754554B2 Methods for fabricating low contact resistance CMOS circuits Electricity 1 Active
US8357575B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers Electricity 0 Active
US7384877B2 Technique for reducing silicide defects by reducing deleterious effects of particle bombardment prior to silicidation Electricity 0 Expired
US7833874B2 Technique for forming an isolation trench as a stress source for strain engineering Electricity 0 Active
US8188871B2 Drive current adjustment for transistors by local gate engineering Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.