Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition

US8039400B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Frank Koschinsky · Radebeul, DE
• Matthias Lehr · Dresden, DE
• Holger Schuehrer · Dresden, DE

Key dates

• Filing date: Apr 6, 2009
• Grant date: Oct 18, 2011
• Expiry date: Jun 20, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.