Patent · US Active

Load page table entry address instruction execution based on an address translation format control field

US8041923B2 · kind B2 · utility

22Cited by

21References

24Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Dan F. Greiner · San Jose, US
Lisa C. Heller · Rhinebeck, US
Damian L. Osisek · Vestal, US
Erwin Pfeffer · Eppelheim, DE
Timothy J. Slegel · Staatsburg, US
Gustav E. Sittmann, III · Webster Groves, US

Key dates

Filing date	Jan 11, 2008
Grant date	Oct 18, 2011
Priority date	—
Expiry date	Jan 28, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/652
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.