Patent · US Active

Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

US8048811B2 · kind B2 · utility

152Cited by

7References

24Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Frank Feustel · Dresden, DE
Thomas Werner · Radebeul, DE
Juergen Boemmels · Heverlee, BE

Key dates

Filing date	Jan 16, 2009
Grant date	Nov 1, 2011
Priority date	—
Expiry date	Jan 16, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2221/1063
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.