Stress-engineered resistance-change memory device
US8049305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jun 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.