Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device
US8053808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2007 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Feb 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A semiconductor power device supported on a semiconductor substrate includes a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a source metal connected to the source region, and a gate metal configured as a metal stripe surrounding a peripheral region of the substrate connected to a gate pad wherein the gate metal and the gate pad are separated from the source metal by a metal gap. The semiconductor power device further includes an ESD protection circuit includes a plurality of doped polysilicon regions of opposite conductivity types constituting ESD diodes extending across the metal gap and connected between the gate metal and the source metal on the peripheral region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.