Standing chip scale package
US8053891B2 · kind B2 · utility
5Cited by
7References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Dec 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.