Integrated circuit and method of fabrication thereof
US8058123B2 · kind B2 · utility
7Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2007 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Apr 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.