Method for fabricating multi-resistive state memory devices
US8062942B2 · kind B2 · utility
15Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.