Stacked integrated circuit package system and method for manufacturing thereof
US8067268B2 · kind B2 · utility
23Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2010 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | May 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.