Transistor with embedded Si/Ge material having reduced offset to the channel region

US8071442B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Stephan Kronholz · Dresden, DE
• Markus Lenski · Dresden, DE
• Andy Wei · Queensbury, US
• Andreas Ott · Erfurt, DE

Key dates

• Filing date: Sep 2, 2009
• Grant date: Dec 6, 2011
• Expiry date: Sep 2, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.