3D channel architecture for semiconductor devices

US8072027B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Suku Kim · Singapore, SG
• Dan Calafut · San Jose, US
• Ihsiu Ho · Salt Lake City, US
• Dan Kinzer · Panguitch, US
• Steven Sapp · Felton, US
• Ashok Challa · Sandy, US
• Seokjin Jo · South Jordan, US
• Mark Larsen · Excelsior, US

Key dates

• Filing date: Jun 8, 2009
• Grant date: Dec 6, 2011
• Expiry date: Jan 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.