Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8076184B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2010 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Aug 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base carrier and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base carrier. A portion of the second surface of the base carrier is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.