Methods for fabricating MOS devices having highly stressed channels

US8076209B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Frank Bin Yang · Mahwah, US
• Rohit Pal · Fishkill, US
• Michael Hargrove · Clinton Corners, US

Key dates

• Filing date: Apr 30, 2010
• Grant date: Dec 13, 2011
• Expiry date: Apr 30, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses.