Structures for and method of silicide formation on memory array and peripheral logic devices
US8076708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.