Semiconductor memory comprising dual charge storage nodes and methods for its fabrication
US8076712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2010 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/697
Abstract
A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.