Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates
US8082423B2 · kind B2 · utility
4Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2005 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | May 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.