Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop

US8084304B2 · kind B2 · utility

Assignee

• Alpha and Omega Semiconductor, Ltd. · US

Inventors

• Mengyu Pan · Shanghai, CN
• Zengyi He · Shanghai, CN
• Kaiyu Chen · San Jose, US

Key dates

• Filing date: May 29, 2010
• Grant date: Dec 27, 2011
• Expiry date: May 29, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET includes fabricate numerous trench MOSFETs on a wafer; add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer; add numerous ESD protection modules atop the Si3N4 isolation layer.