Integration of non-volatile charge trap memory devices and logic CMOS devices

US8093128B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• William Koutny · Santa Clara, US
• Sam Geha · Sunnyvale, US
• Igor G. Kouznetsov · San Jose, US
• Krishnaswamy Ramkumar · San Jose, US
• Fredrick B. Jenne · Tracy, US
• Sagy Levy · Jerusalem, IL
• Ravindra M. Kapre · San Jose, US
• Jeremy B. Warren · Draper, US

Key dates

• Filing date: May 22, 2008
• Grant date: Jan 10, 2012
• Expiry date: May 22, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.