Dual trench isolation for CMOS with hybrid orientations
US8097516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.