Patent · US Active

Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors

US8097542B2 · kind B2 · utility

1Cited by

2References

20Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Karsten Wieczorek · Dresden, DE
Manfred Horstmann · Dresden, DE
Peter Huebler · Coswig, DE
Kerstin Ruttloff · Frankenberg/Sachsen, DE

Key dates

Filing date	Oct 29, 2008
Grant date	Jan 17, 2012
Priority date	—
Expiry date	Jan 27, 2030

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P80/30
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.