Apparatus for implementing processor bus speculative data completion
US8103930B2 · kind B2 · utility
3Cited by
13References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.