In-package microelectronic apparatus, and methods of using same
US8110920B2 · kind B2 · utility
6Cited by
4References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 5, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Sep 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.