Patent · US Active

Method for the simultaneous grinding of a plurality of semiconductor wafers

US8113913B2 · kind B2 · utility

11Cited by

12References

29Claims

0Family size

Assignees

Siltronic AG · DE
Peter Wolters GmbH · DE

Inventors

Georg Pietsch · Burghausen, DE
Michael Kerstan · Burghausen, DE
Heiko aus dem Spring · Hamburg, DE

Key dates

Filing date	Mar 14, 2008
Grant date	Feb 14, 2012
Priority date	—
Expiry date	Dec 15, 2030

Classification

Technology area (CPC B)Performing Operations; Transporting
CPC primaryB24B37/12
WIPO fieldMachine tools
WIPO sectorMechanical engineering

Abstract

Simultaneous double-side grinding of a plurality of semiconductor wafers involves positioning each wafer freely in a cutout of one of plural carriers which rotate on a cycloidal trajectory, wherein the wafers are machined between two rotating ring-shaped working disks, each disk having a working layer of bonded abrasive, wherein the form of the working gap between working layers is determined during grinding and the form of the working area of at least one disk is altered such that the gap has a predetermined form. The wafers, during machining, may temporarily overhang the gap. The carrier is optionally composed only of a first material, or is completely or partly coated with the first material such that during machining only the first material contacts the working layer, and the first material does not reduce the machining ability of the working layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.