Method for forming double gate and tri-gate transistors on a bulk substrate

US8114746B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Andy Wei · Queensbury, US
• Robert Neil Mulfinger · York Haven, US
• Thilo Scheiper · Dresden, DE
• Thorsten Kammler · Radeberg, DE

Key dates

• Filing date: May 28, 2009
• Grant date: Feb 14, 2012
• Expiry date: Jan 19, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.