Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors

US8129276B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ralf Richter · Dresden, DE
• Kai Frohberg · Meißen, DE
• Holger Schuehrer · Dresden, DE

Key dates

• Filing date: Jan 26, 2010
• Grant date: Mar 6, 2012
• Expiry date: Mar 14, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0133
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.