Method to deposit conformal low temperature SiO2

US8129289B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• John Smythe · Boise, US
• Gurtej S. Sandhu · Boise, US
• Brian J. Coppa · Eagle, US
• Shyam Surthi · Boise, US
• Shuang Meng · Austin, US

Key dates

• Filing date: Oct 5, 2006
• Grant date: Mar 6, 2012
• Expiry date: Jun 8, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0228
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.